1. Field of the Invention
The invention relates generally to a method for manufacturing a semiconductor memory device and, more particularly, to a method for manufacturing a semiconductor memory device using asymmetric junction ion implantation.
2. Description of the Related Art
Rapid development in the technology of increasing the degree of integration on semiconductor memory devices has caused a rapid decrease in channel length of transistors in such devices. As the channel length is decreased, operating characteristics of the device deteriorate due to various problems caused by a short channel effect. For example, a decrease of the channel length causes an increase in intensity of electric field near a drain region, which in turn generates hot carriers, thereby deteriorating the operating characteristics and stability of the device. In another example, for a semiconductor memory device such as dynamic random access memory (DRAM), the increase in intensity of electric field in a cell region causes current leakage, which in turn deteriorates refresh characteristics of the device.
In order to suppress the short channel effect as described above, various structures have been suggested, which can increase an effective channel length without decreasing the integration degree of the device. For example, such a structure includes a recess cell structure, and a step gate asymmetric recess structure. For the recess cell structure, a gate stack is formed by forming trenches on a substrate, and then burying the trenches with a gate conductive layer. In this recess channel structure, since the channel is formed along peripheries of the trenches, it has an increased effective length. For the step gate asymmetric recess structure, both sides of a gate stack are asymmetrically disposed by forming a step profile on a substrate, and then forming a gate stack on the step profile. In this step gate asymmetric recess structure, since the channel is formed along the step profile, it also has an increased effective length.
Meanwhile, there is an attempt to improve the refresh characteristics by making a storage node junction region and a bit line junction region to have different impurity concentrations, in addition to employment of such a three-dimensional cell structure. In other words, after forming the gate stack, p-type impurities are implanted by threshold voltage ion implantation to a bit line contact region using a mask layer pattern which allows only the bit line contact region to be exposed. Next, after removing the mask layer pattern, a gate spacer layer is formed, and then source/drain junction ion implantation is performed using a typical method, so that an impurity concentration of a channel region near the storage node junction region is lower than that of a channel region near the bit line junction region, thereby reducing current leakage, and enhancing the refresh characteristics of the device.
Meanwhile, in order to achieve high integration of 100 nm or less, it is necessary to ensure further improved refresh characteristics, and data retention time. However, it is difficult for the conventional method of asymmetric threshold voltage ion implantation to satisfy such requirements.